Dept. Combinational Equivalence Checking Using Satisfiability and Recursive Learning João Marques-Silva Thomas Glass Instituto Superior Técnico Siemens AG Cadence European Labs/INESC Corporate Technology 1000 Lisboa, Portugal 81730 Munich, Germany e-mail: jpms@inesc.pt e-mail: thomas.glass@mchp.siemens.de 6,026,222 (the “'222 Patent”) discloses a combinational equivalence checking method based on a partition of the circuits. In a typical scenario, there are two structurally different implementations of the same design, and the problem is to Mentor Graphics Egypt Ain Shams University Cairo, Egypt Cairo, Egypt Abstract Most recent combinational equivalence checking techniques are based on exploiting circuit similarity. Dept. rithms to the combinational equivalence checking (CEC) problem. Structuralsimilarity of the two designs are exploited by existing BDD, SAT, or ATPG based methods. Combinational equivalence checking (CEC) plays an important role in EDA. We argue that SAT is a more robust and flexi-ble engine of Boolean reasoning for the CEC application than BDDs, which have traditionally been the method of choice. No. Preliminary results on a simple framework for SAT based CEC show a speedup of up to two orders of mag- U.S. Pat. Its immediate application is verifying functional equivalence of combinational circuits after multi-level logic synthesis [6]. Combinational Equivalence Checking Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab. BDD is used for one partition and SAT is used for the other partition. Combinational Equivalence Checking using Boolean Satisfiability and Binary Decision Diagrams Sherief Reda Ashraf Salem Computer & Systems Eng. Abstract: The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This report presents a technique for improving the performance of the existing We give the proof of correctness, and analyze its runtime complexity. 6,086,626 (the “'626 Patent”) disclose a filtering based methods for combinational equivalence checking. We propose a new algorithm, to obtain compact functional representation of threshold elements. U.S. Pat. No. This problem arises in a number of computer-aided design (CAD) applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). of Electrical Engineering Indian Institute of Technology Bombay viren@ee.iitb.ac.in EE 709: Testing & Verification of VLSI Circuits Lecture – 10 (Jan 24, 2012) In In this work we address the problem of combinational equivalence checking for threshold circuits. Combinational equivalence checking is one of the key components in today’s hardware verification methodology. We introduce the notion of combinational equivalence to relate two speed-independent asynchronous (sequential) circuits: a “golden” hazard-free circuit C 1 and a “target” circuit C 2 that can be derived from C 1 through only combinational decomposition and extraction.